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VLSI Fault Modeling and Testing Techniques
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VLSI Fault Modeling and Testing Techniques Hardcover - 1993

by George W. Zobrist; George W. Zobrist (Editor)


From the publisher

VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.

Details

  • Title VLSI Fault Modeling and Testing Techniques
  • Author George W. Zobrist; George W. Zobrist (Editor)
  • Binding Hardcover
  • Pages 208
  • Volumes 1
  • Language ENG
  • Publisher Bloomsbury Publishing PLC
  • Date 1993-01-01
  • Illustrated Yes
  • ISBN 9780893917814 / 0893917818
  • Weight 0.91 lbs (0.41 kg)
  • Dimensions 8.5 x 5.5 x 0.63 in (21.59 x 13.97 x 1.60 cm)
  • Library of Congress Catalog Number 92-23433
  • Dewey Decimal Code 621.395

About the author

brist /f George /i W.

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VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)
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VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)
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VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)

by Zobrist, George W

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